In low-dropout linear regulator (LDO) design, especially a design with high power supply ripple rejection (PSRR) and low noise product, compensation becomes more difficult due to high open-loop gain and limited pole and pole separation. A known approach to this problem is to use an adaptive phase-lead compensation circuit that includes a capacitor in series with a resistor, such that the capacitor provides the Miller Effect and the resistor provides a fixed zero in the frequency domain. This approach, however, does not enhance the phase margin much because the load current is not fixed, especially when a no load condition is presented. Another known approach is to use a transistor (e.g., PMOS) to sense the load current so it can work as an adaptive resistance connected to a voltage supply (VCC). The drawback of this approach is that the Miller Effect cannot be used.